Clock to Chip
- Upcoming
Clock to Chip
Workshop on Static Timing Analysis and PnR
April 18, 2026
09:00 AM
- 05:00 PM
About This Event
IEEE CEDA in collaboration with SILICON (Dept. of ECE) and Dept. Of EEE presents
Clock To Chip
Workshop on Static Timing Analysis (STA) & Placement and Route (PnR).
Turn your RTL dreams to silicon reality!
Distinguished Speakers
- Mayuresh Joshi - Senior Engineer, MediaTek
- Abhishek Kumar Singhania - Physical Design Engineer, Qualcomm
Lunch and snacks will be provided.
IEEE goodies included.
Open to ALL branches.
Registration Fees
- IEEE CEDA Member: ₹150
- IEEE Member: ₹200
- Non-IEEE Member: ₹250
(GST not included)
Registration Deadline: April 16, 2026 (Thursday)
Register Here
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