BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//PES University Events//EN
BEGIN:VEVENT
UID:event-11065@pesevents
DTSTAMP:20261025T120347Z
DTSTART:20241202T093000
DTEND:20241202T123000
SUMMARY:TL-Verilog to Create a RISC-V CPU Core
DESCRIPTION:Ft. Steve Hoover\, Redwood EDA
END:VEVENT
END:VCALENDAR