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TL-Verilog to Create a RISC-V CPU Core
Ft. Steve Hoover, Redwood EDA
December 02, 2024
09:30 AM
- 12:30 PM
About This Event
Join Redwood EDA's founder, Steve Hoover, for hands-on experience with RISC-V, TL-Verilog, and the Makerchip IDE. In hands-on session you'll code core components of a RISC-V subset CPU and see it executing a test program--fetching instructions, decoding them, reading values from registers, etc.You'll learn digital logic essentials and basic CPU microarchitecture through the lens of the Makerchip IDE.
Speaker: Steve Hoover, Founder of Redwood EDA Shrewsbury, Massachusetts, United States
Note: Participants must bring their own laptop for hands-on activity
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